1. Field of the Invention
The present invention relates to a MIS integrated circuit device of multi-threshold voltage and a circuit design method thereof, and particularly to a MIS (Metal Insulator Semiconductor), more particularly to a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit device of multi-threshold voltage, which is provided with a circuit including a MIS transistor of a low threshold voltage and a MIS transistor of a high threshold voltage for shielding a leak current flowing through the circuit in standby time, and a circuit design method thereof.
2. Description of the Related Art
Recently, there has been a demand for higher speed potable electronic devices and their lower power consumption for long battery life. In CMOS LSIs, because power consumption is proportional to the square of voltage, reducing the power consumption can be achieved by lowering the power source voltage. However, lowering the power source voltage leads to lowering the operating speed of MOS transistors. Thus, improvement of the operating speed has been made by reducing the threshold voltage of MOS transistors.
However, lowering the threshold voltage causes increase in leakage current of MOS transistor in standby time, consequently making it difficult to achieve the lower power consumption. In order to overcome these problems, there has been used a MTCMOS (Multi-threshold Voltage CMOS) as shown in FIGS. 7(A) and 7(B).
In FIG. 7(A), a logic circuit 10 including MOS transistors of a low threshold voltage is connected between a supply line of a virtual power source voltage V_VDD and a supply line of a ground voltage VSS, and a PMOS transistor T1 of a high threshold voltage for shielding the leak current is connected between the supply line of the virtual power source voltage V_VDD and a supply line of a power source voltage VDD. In active time, the power control signal *PCNT is made low, turning on the PMOS transistor T1, and thereby the voltage of the V_VDD supply line becomes VDD, for example 1.8V. On the other hand, in standby time, a power control signal *PCNT is made high, turning off the PMOS transistor T1, and thereby the leak current of the logic circuit 10 is shielded.
Referring to FIG. 7(B), a PMOS transistor T2 of the high threshold voltage for shielding the leak current is connected between a supply line of the virtual power source voltage V_VDD and a supply line of the power source voltage VDD, and a NMOS transistor T3 of the high threshold voltage for shielding the leak current is connected between a supply line of the virtual ground voltage V_VSS and a supply line of the ground voltage VSS. In active time, complementary power control signals *PCNT and PCNT are made low and high, respectively, turning on the PMOS transistor T2 and the NMOS transistor T3. On the other hand, in standby time, the power control signals *PCNT and PCNT are made high and low, respectively, turning off the PMOS transistor T2 and the NMOS transistor T3, and thereby the leak current of the logic circuit 10 is shielded.
The following description will be given of only a case having the leak-current-shielding circuit of FIG. 7(A), but the same applies to a case having the leak-current-shielding circuit of FIG. 7(B).
As shown in FIG. 8, a macro 20 includes N cell rows 21 to 2N. For example, as shown in FIG. 9, each cell low comprises a number of standard cells 31, 32, 33, . . . which include PMOS transistors each having the high threshold voltage for shielding the leak current, each gate being supplied with *PCNT, and logic gates including MOS transistors each having the low threshold voltage. Alternatively, as shown in FIG. 10, each cell row comprises a standard cell 30 which only include a PMOS transistor having the high threshold voltage for shielding the leak current, and standard cells such as a NAND gate cell 31A, an inverter cell 32A, . . . which include MOS transistors each having the low threshold voltage. There are disposed a plurality of standard cells 30 for shielding the leak current in one cell row.
In a case where a macro is purchased as IP (Intellectual Property) from other company, if the macro does not include a MOS transistor for shielding the leak current, the MOS transistor must be inserted as shown in FIG. 9 or 10. Also when the macro includes MOS transistors for shielding the leak current, the MOS transistor for shielding the leak current must be removed from each cell, or cells for shielding the leak current must be removed from each cell row in order to achieve higher integration, at the sacrifice of decrease of power consumption in standby time.
In addition, in the case of the circuit shown in FIG. 9, because the gate width of the leak-current-shielding MOS transistor is determined by considering a margin in current flowing through the logic gate, in order not to hinder the improvement of speed for each logic gate, the margin in the entire circuit becomes excessively large, increasing the macro-occupied area on the substrate. In case of the circuit shown in FIG. 10, because no logic gate is included in the leak-current-shielding cell, useless area becomes increased, thereby increasing the macro-occupied area on the substrate.